White Papers

Read the following whitepapers to further understand the different applications of S2C technology used by our customers and partners.


Employing Multi-FPGA Debugging Techniques

Debugging a single FPGA design is a relatively simple task. However, performing debug operations on a multi-FPGA platform is an extremely long and often labor-intensive process. Manual techniques only allow for debugging one FPGA at a time and traditional tools such as an external logic analyzer or FPGA internal logic analyzer have limitations when it comes to multi-FPGA debug. With manual processes, only gaining insight into the behavior of one FPGA at a time may result in missed design errors or misleading design behavior as it becomes difficult to test the functionality of the design as a whole. The part of a design that resides on a particular FPGA may be bug-free in its compartmentalized form, but when operated within the totality of the design may contain critical errors. External Logic analyzers have a limited number of probes and require designers to pull their probes to the top level so they come out from the FPGAs’ I/O pins. Because of these issues, debug has been largely inadequate within the FPGA prototyping process thus leaving debug to be done only through simulation and/or emulation.
But hold on a minute. There have been significant advances in FPGA prototyping to deal with the very complex issue of multi-FPGA debug that augment the FPGA Prototyping Flow.



Choosing the best pin multiplexing method for your multiple FPGA partition

Using multiple FPGAs to prototype a large design requires solving a classic problem: the number of signals that must pass between devices is greater than the number of I/Os pins on an FPGA. The classic solution is to use a TDM (Time Domain Multiplexing) scheme that muxes two or more signals over a single wire or pin.
This solution is still widely employed, and coupled with the advances in FPGAs, the obstacles to constructing a multi-device prototype are greatly reduced. The latest FPGAs offer advantages such as a very high number of industry-standard I/O, integrated high-speed transceivers, and LVDS signaling.



FPGA Prototyping Primer

FPGA prototyping is the methodology to prototype SoC and ASIC designs on FPGAs for hardware verification and for early software development. This methodology is sometimes referred also as ASIC prototyping or SoC prototyping.
Prototyping SoC and ASIC designs on FPGAs has become a mainstream verification methodology for hardware design as well as a method for early software and firmware co-design. This primer on FPGA prototyping will discuss the important factors of why to prototype, the current challenges of prototyping and how to overcome them, and the issue of building your own or adopting an off-the-shelf prototyping solution.



Getting the Most Out of FPGA Prototyping

Whether you are designing or verifying extremely complex cutting edge designs or more mainstream design, FPGA prototyping can help you achieve your goals with maximum benefit. The key to getting the most out of FPGA prototyping requires a good understanding of how this technology works and the FPGA prototyping solutions that match your design and verification requirements. This eBook contains of series of articles published in EE Times that can help you navigate the world of FPGA prototyping technology – everything from overcoming FPGA prototyping hurdles to expanding the use of your FPGA prototype upstream of the design flow to using FPGA prototyping for even the largest designs. The eBook also gives you insight into how a complete prototyping platform can help for any design stage, any design size, and with enterprise-wide access, anytime, anywhere.



FPGA Prototyping of System-on-Chip Designs

The Need for a Complete Prototyping Platform for Any Design Size, Any Design Stage with Enterprise-Wide Access, Anytime, Anywhere

The FPGA prototyping system must offer enterprise-wide accessibility ― a complete prototyping platform is one that operates at any functional design stage, with any design size, and across multiple geographical locations. All of these capabilities must be available on demand and remotely-accessible at all times. Such an approach would significantly increase engineering productivity and reduce the end-product’s time to market, while increasing its return on investment (ROI), as well as increasing the lifetime ROI of the FPGA prototyping platform itself.
This paper addresses how the FPGA prototyping system must evolve into a complete prototyping platform to meet the ever-growing SoC design challenges. Specifically, the paper:

  • Reviews the growing challenges in SoC development.
  • Examines the ability of current FPGA prototyping approaches to meet these challenges effectively.
  • Outlines the requirements for FPGA prototyping solutions to meet these challenges.


Exercising H.264 Video Compression IP Using Commercial FPGA Prototypes

Increasingly silicon IP vendors are utilizing FPGA prototypes as the vehicles for both pre-sales and post-sales support of their IP cores. FPGA prototypes facilitate IP vendors to allow their potential customers to see and evaluate their IP securely at near real-time speed. The FPGA prototype also can serve as a reference design for customers to speed up their design process after the IP transaction is complete. This whitepaper describes how CAST has selected S2C’s TAI Logic Module, a commercial FPGA prototyping tool, to build their H.264 Encoder IP demonstration platform.



A Multi-FPGA Based Platform for emulating a 100M-transistor-scale Processor with High-speed Peripherals

This published paper describes how Institute of Computing Technology (ICT), Chinese Academy of Science used S2C Dual Virtex-5 TAI Logic Modules to prototype a 100 million transistor-scale processor at 25MHz to boot unmodified operating system for carrying out a variety of architectural explorations. The paper identified several key challenges when prototyping a complex design onto multiple FPGA devices and how the ICT research engineers were able to solve these challenges including FPGA partitioning, pin limitations, emulating high-speed IO and debugging the design on S2C’s TAI Logic Module.



Design SoC using FPGA-based IP – An FPGA-Based SoC Design Methodology

SoC design methodology has greatly matured over the past decade and many obstacles have been solved by improved semiconductor technologies, better EDA tools, and new design Servicess. Also thanks to the rapid development of silicon IP industry, designers today can buy most of the design blocks required in an SoC in the market. Nevertheless, putting these IP blocks in an optimal way becomes a key issue, especially when we need to consider system level issues such as performance, bandwidth and power. Moreover, as software content for an SoC continues to enlarge, the ability to co-design software and hardware early becomes a necessity. This whitepaper describes a design methodology that utilizes FPGA-based IP models to create early system prototypes at near real-time speed that allow early software and hardware co-design. Be the first one to the market with the right SoC product by adopting the FPGA-based electronic system level (ESL) methodology.