Prodigy Player Pro
Cockpit for Prototype Design and Multi-Debug Set Up
Prodigy Player Pro is a tool that works with the FPGA-based prototyping platforms from S2C. Prodigy Player Pro plays three roles in speeding your development process – it configures the prototype, runs remote system management and provides set up for multi-FPGA debugging.
- Faster partition engine supporting billion gate designs
- Enhanced pin-multiplexing macro increases system performance up to 50%
- Flexible pin-multiplexing ratios across multiple clock domains
- Up to 70% time saving via optimized black-box flow
- Fully automate and increase productivity with TCL scripting
An integrated GUI environment and Tcl interface makes it easy to take an existing design, compile it, partition it into multi-FPGAs, and generate the individual bit files.
Automated Compile Flow
Prodigy Player Pro has an intuitive GUI environment to guide all compile steps. After a design is compiled once, you can perform an ECO flow automatically in Tcl mode:
- Import design
- Set up probes
- Run synthesis
- Partition design
- Assign & I/Os
- Run FPGA place and route
- Generate bit file(s)
Prodigy Player Pro provides a library of S2C daughter board pin-map files, and automatically matches them to I/O connectors. GUI-based clock and I/O properties assignment minimizes chance of error.
- Automatic and guided partitioning to multiple boards
- User-guided performance optimization
- User configurable cable connection setup
- Black-box approach to save partitioning time
- Enhanced system performance by TDM optimization
- Pre-qualification of signals before automatic pin-multiplexing insertion
- Timing estimation to quickly understand the performance before place and route
For compiled designs, Prodigy Player Pro enables you to control the target Prodigy Logic Module or Prodigy Logic System directly from the same software console, through either Ethernet or USB connections. The lock/unlock mechanism allows multiple users to use one system simultaneously.
Multiple FPGA Configurations
Prodigy Player Pro can download the design to the FPGA(s) through USB or Ethernet. It can also write the design to an SD card on the Prodigy Logic Module/System and download the design from an SD card.
Remote System Control
All system features can be controlled remotely through USB or Ethernet.
- Automatic detection of daughter cards when plugged in
- Easy monitoring I/O voltages, currents and temperatures
- Controlling multiple Prodigy Logic Modules/Systems conveniently from one console
A step-by-step wizard enables users to check for potential broken I/O pins, interconnection nets and clock lines. Users can also verify the global clock frequencies and I/O voltage settings.
Virtual “SWs & LEDs”
Prodigy Player Pro provides virtual switches and indicators that you can use just like real hardware.
- Virtual LEDs for quick monitoring of design status
- Virtual push buttons and switches to set design input conditions quickly
- Virtual UART for convenient firmware debugging
Debug Set Up
Prodigy Player Pro allows users to pre-select the signals to be observed before compilation and define the trigger conditions to start a data capture. During runtime, the selected signals are captured and stored in an external DDR3/DDR4 memory for analysis.
Integrated In-Circuit Debug Setup
- Preserve internal FPGA probes
- Probes are distributed to multiple FPGAs automatically based on the partition results
- Set up trigger and trace signals in multiple FPGAs from a single console
Trigger Condition Specification
Users can easily set the trigger events and combinational events through the Prodigy Player Pro Debug panel.
- Trigger Events support: ==, !=, >=, <=, >, < and counting
- Combinational Events support: !, &, |, ^, -> and counting
- Supports up to 8 event trigger blocks
Large Number of Probes Without Re-Compile
- Mark an unlimited number of internal FPGA probes
- Trace up to 32K probes per FPGA in 8 groups of 4K probes each without FPGA re-compilation
Concurrent Multiple FPGAs Debug (MDM hardware required)
- Debug multiple FPGAs using a single Logic Analyzer
- Transmit trigger and trace data from multiple FPGAs to MDM through high-speed transceivers
- Write the sample data in VCD/FSDB format for analysis
- Store large external 8GB of waveform
- Compile: VU, KU, S10 and A10
- Runtime: VU, KU, S10 and A10
- Debug Set Up: VU, KU and S10
- Windows 7/10 64-bit
- Red Hat Enterprise Linux 6.6/7.6 64-bit
- Ubuntu Linux 14.04/16.04 64-bit
- CentOS 7.4 64-bit
- Synthesizable RTL (Verilog, VHDL, System Verilog)
- Synthesizable gate-level netlist
- Mixed languages