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S2C provides complete design and verification services based on FPGA prototyping. Let S2C's extensive experience and proven results work for you in your next design challenge.

Prototyping

    • High performance and high density
    • Automatic partitioning
    • Deep trace debug
    • Flexible & powerful I/Os
01

Emulation

    • Up to 1 billion ASIC gates
    • Fast compilation functions
    • Full visibility
    • Support ICE/SBA/TBA
02

Simulation

    • Flexibly design in various ways
    • Cycle and event driven mode
    • High speed simulation engine
    • Advanced modeling interface
03

Formal

    • RTL code analysis
    • Logic equivalent check
    • Vacuous assertion check
    • Verification progress and coverage measurement
04

Modeling

    • Architecture design
    • System performance analysis logic equivalent check
    • Virtual devices
    • IP modeling in early design stage
05

検証ツール比較

The increasing size and complexity of SOC/ASIC designs have led to an exponential increase in the complexity of validation. In order to reduce time to market, it is important to choose different verification tools in different design stages to improve efficiency and accelerate the convergence of verification.

All
Simulation
Emulation
Prototyping
設計と検証のプロセス
Design Verification Process
Architecture Design
IP Development
SoC Integration
System Testing
Tape-out
Architecture Design
Simulation
Emulation
Prototyping
Formal
Heterogeneous Verification
Architecture Design
IP
Development
SoC
Integration
System
Testing
Tape-out
Rapid architecture design & System performance analysis & Software and hardware co-design
Shorten the design cycle
 
ヘテロジニアス検証プラットフォーム

S2C's Prodigy Prototyping technology provides industry-leading remote management capabilities, ranging from remote FPGA download, virtual IOs, switches, UARTs & LEDs and remote power cycles, to enterprise-class server/client management software, to provide effective resource sharing and management.

  • Design architecture planning, system performance analysis, virtualization application scenarios and IP modeling in the early stage
  • Support System Verilog, Verilog, VHDL RTL level simulation
  • Early simulation verification without a complete RTL design
  • Hardware simulation accelerates super-large design simulation speed and supports automatic compilation and full signal visibility
  • High-performance prototype verification for early software development and extensive system testing
  • Use transaction-level interfaces to reduce test program development time while ensuring the accuracy of system results

試作検証プランを入手

どのタイプのチップを設計していますか?
設計に含まれるASICゲートの容量は?
500万~2000万
2,000万~5,000万
5000万~1億
1億~10億
10億以上
どのFPGAを使いたいですか?
ザイリンクス VU440
ザイリンクス KU115
ザイリンクス VU19P
ザイリンクス VU13P
ザイリンクス VU9P
インテル S10-10M
インテル S10-2800
わからない、専門家のアドバイスが必要
どのようなFPGA構成が必要ですか?
シングルFPGA
デュアルFPGA
4 つの FPGA
8つのFPGA
わからない、専門家のアドバイスが必要
どのような周辺機器インターフェースが必要ですか?
プロトタイプ検証プラットフォームはいくつ必要ですか?
以下のツールが必要ですか?
セグメンテーションツール
複数の FPGA デバッグ ツール
コモデリング ツール (FPGA と PC ホスト間で大量のデータをやり取りできます)
当社の製品をいつ使用する必要がありますか?
0~6ヶ月
6-12ヶ月
12ヶ月以上
わからない
その他
参加する
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検証コード

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