製品
S2Cソリューションで市場投入の先陣を

PCIe Gen2x4 Reference Design

This demo shows the feature of the S2C 4-Lane PCIe Gen2 GTX Module running on the S2C Virtex-7 Prodigy Logic Module, which is equipped with GTX connectors to implement the physical interconnect transform between the PCIe interface and the Samtec GTX interface.


The GTX transceivers are probed to GTX connectors on the Virtex-7 Prodigy Logic Module, which run up to 8Gbps allowing for high-speed development and verification with the Virtex-7 Prodigy Logic Module and S2C 4-Lane PCIe Gen2 GTX Module.


The reference design demonstrates the effectiveness of the 4-Lane PCIe Gen2 working with the S2C hardware platform. The PCIe device can be identified on a workstation in either Windows or Linux. Configuration information for the PCIe device, such as lane width, link speed, vendor ID, and subsystem ID, can be read on on the workstation. The S2C 4-Lane PCIe Gen2 GTX Module is downward-compatible with PCIe Gen1 as well. The PCIe Gen1 application can also be developed and verified on the S2C Virtex-7 Prodigy Logic Module.


Features

  • Access to the Block Memory instantiated in the FPGA device using the PCI Express

  • The Xilinx 7 Series Integrated Block for PCI Express solution, which

    • Uses GTXE2 or GTPE2 transceivers for 7 series FPGA families
    • Consists of the Physical, Data Link, and Transaction Layers
    • Supports x1/x2/x4/x8 PCI Express at 2.5Gb/s and 5.0Gb/s
    • Provides full support for 2.5Gb/s and 5.0Gb/s PCI Express Endpoint and Root Port configurations
    • Includes a standardized user interface
  • An AXI Memory Mapped To PCI Express(1.06.a) IP and Block Memory Generator(7.3) IP allows for the software interface to be converted from PCI Express to an AXI interface, and the internal block memory is integrated on the AXI bus.

  • Use of the S2C 4-Lane PCIe Gen2 GTX Module to implement Physical interface transform between the PCIe interface and the Samtec GTX interface.


Applications

  • Data communications networks

  • Telecommunications networks

  • Broadband wired and wireless applications

  • Cross-connects

  • Network interface cards

  • Chip-to-chip and backplane interconnect

  • Crossbar switches

  • Wireless base stations

  • S2C ProtoBridge solution


Block Diagram

image.png


Implementation Results

Xilinx Device

Slices

BRAM

Specific Feature

Virtex-7 2000T

5711

40

PCIE_2_1


Deliverables

The full project for Vivado2012.4 is available, including everything required for successful implementation.  The PCIe Gen2 driver for win7-64bit operation system is supplied.


To run the demo on the S2C Hardware Platform, the following documentation is included:


  • S2C Dual Virtex-7 Prodigy Logic Module Hardware Reference Manual

  • S2C x4 PCIe Gen2 Module Test Instructions for Dual/SingleA V7 Prodigy Logic Module

  • S2C 4-Lane PCIe Gen2 GTX Module Reference Manual

試作検証プランを入手

どのタイプのチップを設計していますか?
設計に含まれるASICゲートの容量は?
500万~2000万
2,000万~5,000万
5000万~1億
1億~10億
10億以上
どのFPGAを使いたいですか?
ザイリンクス VU440
ザイリンクス KU115
ザイリンクス VU19P
ザイリンクス VU13P
ザイリンクス VU9P
インテル S10-10M
インテル S10-2800
わからない、専門家のアドバイスが必要
どのようなFPGA構成が必要ですか?
シングルFPGA
デュアルFPGA
4 つの FPGA
8つのFPGA
わからない、専門家のアドバイスが必要
どのような周辺機器インターフェースが必要ですか?
プロトタイプ検証プラットフォームはいくつ必要ですか?
以下のツールが必要ですか?
セグメンテーションツール
複数の FPGA デバッグ ツール
コモデリング ツール (FPGA と PC ホスト間で大量のデータをやり取りできます)
当社の製品をいつ使用する必要がありますか?
0~6ヶ月
6-12ヶ月
12ヶ月以上
わからない
その他
参加する
電話番号を入力していただければ、すぐに折り返しご連絡いたします
あなたの電話を入力してください
検証コード

This site uses cookies to collect information about your browsing activities in order to provide you with more relevant content and promotional materials, and help us understand your interests and enhance the site. By continuing to browse this site you agree to the use of cookies. Visit our cookie policy to learn more.