Eyes Meet Innovations at DAC
It gives me a very nice, somewhat nostalgic, feeling after attending the 52nd DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D teams’ is less in DAC, unless an engineer has a paper to present. So, I didn’t have many opportunities to attend DAC in the past. Now that I am in consultancy and marketing role, when I attended DAC, I felt it to be overwhelming in terms of dissemination of technological information. I found DAC to be one of the best forums for learning about most of the new innovations in the semiconductor space. We get an opportunity to see the new innovations working through live demos at DAC year after year.
I must confess that I could not see all of it in DAC 2015; missed a few booths even though I had planned to visit them. The environment was so vibrant from the first day that it was difficult to manage time between various presentations, talks, demos, keynotes, invited talks, panel discussions, and so on to attend one after another. The most interesting part I found about the DAC is that it has many facets of opportunities for everyone to avail of what they desire and strive for. One of my agendas in DAC has been to find out the top innovations of the year. This year also, fortunately being physically present at DAC, I found some of the compelling technologies which are going to add great value in the semiconductor ecosystem. This may not be the whole list of top innovations, but here are the ones I could observe myself.
ARM IP Tooling Suite: The ARM IP Tooling Suite provides a very innovative and relevant capability for SoC integration in today’s design environment. The Socrates DE provides a design environment where multiple IPs including third party IPs can be configured and assembled together to optimize your BOM for the SoC. There are CoreSight and CoreLink Creators that help in micro-architecture creation and further improvement in configuration efficiency. The whole estimation and creation can be done in a matter of minutes or hours. This solves one of the key issues in the semiconductor design industry where SoCs have to be targeted according to the market segment and integration of right IPs has to be pre-determined for the success of the SoC. This is a key innovation in today’s context; I will be writing more specifics about this separately, stay tuned.
Veloce + PowerArtist: This is a great example of competitors complimenting their tools for larger benefit of the semiconductor ecosystem. Interestingly this is integration between two competitor tools. Mentor’s Veloce emulator generates real-time dynamic power data for the SoC, and that is read directly by ANSYS’ API for dynamic power analysis in PowerArtist. This approach provides accurate power analysis in order of magnitude lesser time.
JasperGold Formal Verification Platform: Formal and assertion-based verification technologies are gaining ground in SoC verification space. Designers are not able to use them in the main stream verification, primarily due to lack of ease-of-use. JasperGold platform solves the ease-of-use problem by offering automated ‘Verification Apps’ and seamlessly integrating them with the Incisive Verification Platform and Cadence System Development Suite where coverage driven verification methodology takes place and verification gets further complemented by simulation, emulation and debugging environment.
Cloud Cube: The Cloud Cube 32 is an innovative solution from S2C that enables FPGA-based prototyping of large SoCs of sizes up to 1.4 billion gates. It provides a complete prototyping platform that lets designers start the design at any stage, from anywhere in the world and the design size can grow up to any extent with this scalable architecture.
GENUS: A new generation RTL compiler from Cadence that has a massively parallel architecture providing order of magnitude faster synthesis and significant improvement in PPA over previous solution.
IC Compiler II: A major improvement in Synopsys’ IC Compiler for order of magnitude higher throughput and better QoR of placement and routing.
Spice Simulation and DFY tools in the cloud: This is a novel idea from ProPlus Design Solutions, Runtime Design Automation and Zentera Systems where NanoSpice and NanoYield are managed by NetworkComputer workload manager from Runtime DA and run on a public cloud managed and secured by Zentera’s Hybrid Cloud Solution over virtual network.
These are some of the new innovations of this year. Also, there are good innovative products from previous years which are proving to be valuable by now. We are seeing good new acquisitions as well that are expected to drive more innovations in future. Some of the innovations from past acquisitions (e.g. Jasper acquisition by Cadence) are already visible today. I also learnt about other innovations from past acquisition that are in work and expected to come out soon; will write more about those later.