Get to market first with S2C solutions
White paper: Design SoC using FPGA-based IP – An FPGA-Based SoC Design Methodology

SoC design methodology has greatly matured over the past decade and many obstacles have been solved by improved semiconductor technologies, better EDA tools, and new design Servicess. Also thanks to the rapid development of silicon IP industry, designers today can buy most of the design blocks required in an SoC in the market. Nevertheless, putting these IP blocks in an optimal way becomes a key issue, especially when we need to consider system level issues such as performance, bandwidth and power. Moreover, as software content for an SoC continues to enlarge, the ability to co-design software and hardware early becomes a necessity. This whitepaper describes a design methodology that utilizes FPGA-based IP models to create early system prototypes at near real-time speed that allow early software and hardware co-design. Be the first one to the market with the right SoC product by adopting the FPGA-based electronic system level (ESL) methodology.

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White paper: Exercising H.264 Video Compression IP Using Commercial FPGA Prototypes

Increasingly silicon IP vendors are utilizing FPGA prototypes as the vehicles for both pre-sales and post-sales support of their IP cores. FPGA prototypes facilitate IP vendors to allow their potential customers to see and evaluate their IP securely at near real-time speed. The FPGA prototype also can serve as a reference design for customers to speed up their design process after the IP transaction is complete. This whitepaper describes how CAST has selected S2C's TAI Logic Module, a commercial FPGA prototyping tool, to build their H.264 Encoder IP demonstration platform.

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White paper: Choosing the best pin multiplexing method for your multiple FPGA partition

Using multiple FPGAs to prototype a large design requires solving a classic problem: the number of signals that must pass between devices is greater than the number of I/Os pins on an FPGA. The classic solution is to use a TDM (Time Domain Multiplexing) scheme that muxes two or more signals over a single wire or pin. This solution is still widely employed, and coupled with the advances in FPGAs, the obstacles to constructing a multi-device prototype are greatly reduced. The latest FPGAs offer advantages such as a very high number of industry-standard I/O, integrated high-speed transceivers, and LVDS signaling.

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White paper: A Multi-FPGA Based Platform for emulating a 100M-transistor-scale Processor with High-speed Peripherals

This published paper describes how Institute of Computing Technology (ICT), Chinese Academy of Science used S2C Dual Virtex-5 TAI Logic Modules to prototype a 100 million transistor-scale processor at 25MHz to boot unmodified operating system for carrying out a variety of architectural explorations. The paper identified several key challenges when prototyping a complex design onto multiple FPGA devices and how the ICT research engineers were able to solve these challenges including FPGA partitioning, pin limitations, emulating high-speed IO and debugging the design on S2C's TAI Logic Module.

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Request for Quote

What type of chip are you designing?
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
Not sure, need professional advice
What kind of FPGA configuration do you need?
Single FPGA
Four FPGAs
Eight FPGAs
Not sure, need professional advice
What kind of peripheral interface do you need?
How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
When do you need to use our products?
0-6 months
6-12 months
More than 12 months
Not sure
Any additional comments?
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