Webinar: Debugging Techniques for FPGA Prototyping
Jul 22, 2021

Webinar: Debugging Techniques for FPGA Prototyping


Already familiar with FPGA debugging? How would it apply to FPGA prototyping, especially over multiple FPGAs? Find out what #S2C has to offer in this 8-minute video.

    • Time: Octotber 09, 2021 (CST)

    • Location: Online


     


    Details about Webinar:

      • Basic debugging techniques such as VIO IP & Source/Probes Editor are available from FPGA vendors

      • Internal/Embedded Logic Analyzer available in Vivado/Quartus                    

        -Only support single FPGA debug and consumes FPGA resources

      • S2C offers additional FPGA prototyping debugging approaches to increase your high productivity

        -Basic IO, UARTs and Virtual IOs -ProtoBridge to offer high bandwidth AXI connectivity over PCIe

        -NT Bus to offer mid bandwidth connectivity AXI over Ethernet

        -MDM Pro to provide concurrent data sampling over multiple FPGAs

        -Over 90+ daughter cards to support in-system testing and protocol connectivity

Request for Quote

What type of chip are you designing?
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
Not sure, need professional advice
What kind of FPGA configuration do you need?
Single FPGA
Dual FPGA
Four FPGAs
Eight FPGAs
Not sure, need professional advice
What kind of peripheral interface do you need?
How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
When do you need to use our products?
0-6 months
6-12 months
More than 12 months
Not sure
Any additional comments?
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