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Ethernet TCP IP reference design

The TCP/IP Demo is aimed at demonstrating the features of S2C's 2 Channel Gigabit Ethernet PHY Interface Module running on both the S2C Virtex-7 Prodigy Logic Module and the S2C Kintex-7 Prodigy Logic Module.

The Demo design is based on a MicroBlaze processor, using ISE14.5 EDK tools to integrate external memory (DDR3) and an Ethernet MAC controller with an AXI4 and AXI4 Lite bus. The Ethernet MAC controller communicates with the Ethernet MAC PHY chip(Marvell 88E1111) on S2C's 2 Channel Gigabit Ethernet PHY Interface Module, which is 10/100/1000BASE-T IEEE 802.3 compliant and supports both GMII and RGMII interfaces. The network configurations and interactive data between processor and user application are accessed from and stored in DDR3 memories on S2C's 1GB DDR3 Memory Module for the K7 Prodigy Logic Module.

The hardware platform, including the Prodigy Logic Module and daughter modules, sets up the network environment. Then, iperf running on a PC is used to test the network performance either for 10Mb/s or 100Mb/s.

The network endpoints run on a hardware platform and PC working in Server-Client mode, either as a Server or a Client. Multiple configurations can be set in iperf, such as port number, report interval and TCP window size. A bandwidth graph and status messages are supplied for users to look up the network performance.


Based on a MicroBlaze Processor, the reference design can be used to test the TCP connection performance of 10Mb/s or 100Mb/s network. Features include:

  • AXI Ethernet Lite MAC(v1.01.b) IP to implement MAC functions

    • Supports the IEEE Std.802.3 Media Independent Interface(MII) to industry standard Physical Layer(PHY) devices
    • Communicates with a processor using the AXI4 interface
    • Provides a 10Mb/s and 100Mb/s interface
    • Provides the minimal functions necessary to provide an Ethernet interface with the least amount of resources used
  • External memory(DDR3) for mutual data storage

  • AXI 7 Series Memory Controller IP

  • Iperf tool to measure network performance

    • Provides flexible configurations and GUI to show the performance of the network under test
    • Measures bandwidth
    • Reports MSS/MTU size and observed read sizes
    • Supports TCP window size via socket buffers
  • The software (iperf) in the PC and embedded design running on the S2C Virtex-7 Prodigy Logic Module works in Server-Client mode, and vice versa.


The reference design can be used to test the Ethernet Interface performance. It can also be applied to the TCP performance tests of 10Mb/s or 100Mb/s network, and to targeted applications such as the Network Interface Adapter, MAU, CNR and ACR etc.

Block Diagram

Block Diagram


Both XPS and SDK projects are available, and include everything required for successful implementation.

To run the demo on the S2C Hardware Platform, related documentation is included:

  • Instructions for TCI/IP Demo running on K7-325T Prodigy Logic Module

  • Kintex-7 Prodigy LM Hardware Reference Manual

  • S2C 2 Channel Gigabit Ethernet PHY Interface Module Reference Manual

  • S2C 1GB DDR3 Memory Module for the K7 Prodigy Logic Module Reference Manual

Additionally, the iperf installation package is enclosed with the latest version accessible from

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What type of chip are you designing?
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
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Xilinx VU440
Xilinx KU115
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Xilinx VU13P
Xilinx VU9P
Intel S10-10M
Intel S10-2800
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How many prototype verification platforms do you need?
Do you need the following tools?
Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
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