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DDR3 Reference Design

At the core of the Xilinx® 7 series FPGA memory interface solutions are a combined pre-engineered controller and physical layer (PHY) for interconnecting the 7 series FPGA user designs and AMBA® advanced extensible interface (AXI4) slave interfaces with DDR3 SDRAM devices.


  • Component support for interface widths up to 64 bits 

  • Optional AXI4 slave interface

  • Single and dual rank SODIMM support 

  • 1, 2, 4, and 8 GB density device support 

  • 8-bank support 

  • 8:1 DQ:DQS ratio support 

  • 8-word burst support 

  • On-die termination (ODT) support 

  • ZQ calibration – initial and periodic (configurable) 

  • JEDEC®-compliant DDR3 initialization support 

  • Source code delivery in Verilog and VHDL (top-level files only) 

  • 4:1 and 2:1 memory to FPGA logic interface clock ratio 


The MIG core is used to connect a user design to a DDR3 SDRAM device. The physical layer (PHY) side of the design is connected to the DDR3 SDRAM device through FPGA I/O blocks (IOBs), and the user interface side is connected to the user's design through FPGA logic.

Block Diagram


Functional Description

The top-level functional blocks of the Xilinx 7 series FPGAs memory interface solution include:

  • The User Interface block:

    • Presents the user interface to a user design

    • Provides a simple and user-friendly alternative to the native interface

    • Buffers read and write data

    • Reorders read return data to match the request order

    • Presents a flat address space and translates it to the addressing required by the SDRAM

  • The Memory Controller block:

    • Receives requests from the user design

    • Reorders requests to minimize dead states for maximum SDRAM performance

    • Manages SDRAM row/bank configuration

    • Performs high-level SDRAM management such as refresh and activate/precharge

  • The PHY block:

    • Interfaces with the Memory Controller block over a simple interface and translates the signals into the actual signals sent to the SDRAM, and vice versa

    • Translates and synchronizes control and data over various clock domains

    • Initializes the SDRAM

    • Performs write leveling for DDR3 (fly-by routing topology required for component designs)

    • Performs calibration to center align capture clocks with read data

  • An example user design is provided with the core as well

Implementation results

The DDR3 MIG core has been tested on Prodigy V7 Logic Module series. The following are the DDR3  Implementation results on xc7v2000tflg1925.

Slice LUTs: 22406(1.83% of total)

Slice Registers: 21171(1.51% of total)

Max data rate on-board: 1333Mbps


The reference design is provided as a whole Xilinx Vivado project(implemented), which includes:

  • Generated MIG IP core with all the DDR3 configuration information(by opening MIG wiward)

  • RTL source code generated by MIG

  • XDC files that include the DDR3 pin location and timing constraint information

  • A readme text file that shows how to run step by step on board

  • Document of 7 Series Devices Memory Interface Solutions user guide

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