S2C's new FPGA-based TAI Verification Module for ASIC/SoC prototyping | EE Times
Jun 16, 2011

Max Maxfield  6/16/2011 04:14 PM EDT

Editor's Note: See also Brian Bailey's recent blog:" A prediction ahead of its time? " about the FPGA-based prototyping systems he saw at DAC, including the offerings from S2C.


At DAC last week, the folks at S2C Inc., specialists in rapid SoC/ASIC prototyping solutions, announced that they have developed the TAI Verification Module (patent pending). This is a prototype verification product that allows user designs in FPGA-based prototypes to be verified with massive and fast testbenchs via a x4 PCIe Gen2 channel to the PC.

The Altera Stratix-4 GX FPGA-based TAI Verification Module has integrated Altera SignalTap Logic Analyzer with S2C's TAI Player software enabling concurrent debugging of multi-FPGA design using the RTL names. This innovative technology supports set up of multiple groups of 480 probes during design compilation so the user can view thousands of RTL-level probes in multiple FPGA without requiring lengthy FPGA recompilation.

"We have been working closely with our customers since 2003. We noticed that many customers wanted to transfer large amounts of verification data to and from their FPGA-based prototypes. In addition, most customers implement their verification debug with the FPGA vendor tools and more recently, with new third-party tools. One of the limitations of the FPGA vendor tools is that they only allow you to debug one FPGA at a time. This is fine for single FPGA solutions, but is very limiting for multiple FPGA solutions like our new 32.8 million gate 4 FPGA Quad S4 TAI LM that we released in April 2011. We came with the idea for the Verification Module that enables the bi-directional high speed data transfer between the FPGA-based prototype and the user’s verification environment using a x4 PCIe Gen 2 channel. The TAI Verification Module also allows the user to simultaneously look at signals from multiple FPGAs" said Mon-Ren Chene, S2C's Chairman and CTO.

Three modes of operation The S2C S4 TAI Verification Module provides three usage modes: Verification Mode, Debug Mode and Logic Mode. The Verification Mode enables the transfer of large amounts of data from/to a PC through a x4-lane PCIe Gen2 interface using SCE-MI or customizable C-API. In the Debug Mode, the S4 TAI Verification Module enables simultaneous debugging of multiple FPGAs using Altera SignalTap while maintaining the user's RTL net names. The user can prototype a design with capacity up to 3.6M gates in the Logic Mode. All debug and verification setup for the Verification Module is done in the TAI Player Pro software.

  Verification Mode: The verification mode utilizes the TAI Verification Module’s high speed PCIe Gen2 interface to rapidly and bi-directionally transfer large simulation data to and from the TAI Logic Module. This mode can be used to directly connect a prototyping system to a simulator for co-simulation. The user can utilize S2C-provided customizable C-API or can industry standard SCE-MI interface as shown in the following diagrams:



Debug Mode: The Debug Mode utilizes the user's existing Altera SignalTap debug environment. The TAI Verification Module takes user defined signals from the multiple FPGAs in the Logic Module and sends them to the TAI Verification Module where SignalTap is connected through the TAI Verification Module's JTAG interface. The TAI Verification Module plugs directly into the new Quad S4 TAI Logic Module as shown in the photo below:



Maximize Visibility: 120 signals from each FPGA of the Quad S4 Logic Module are routed to the Verification Module's FPGA. The user has the capability of routing 120 x N signals from each of the four Quad S4 Logic Module's FPGAs. For the initial software release, N is fixed at 4 but it will be user defined in future releases. All the user needs to do for set up are select probes in RTL level before design are synthesized and place them in different groups of 120 probes per FPGA, TAI Player Pro automates the multiplexing of pin data and route the debugging signals from multiple FPGA to a single Altera SignalTap in Verification Module, all retaining the RTL names. The debugging data is stored in the Verification Module FPGA memory until preset trigger conditions cause it to be dumped for debug by Altera's SignalTap.


Logic Mode: The S4 TAI Verification Module can be used as a standalone prototyping board for smaller scale SoC or ASIC design for up to 3.6M gate capacity. The S4 TAI Verification Module can mount either the Altera Stratix IV 180 or 360 GX FPGA and has a total of 480 external I/O on 4 LM connectors, x4 PCIe Gen2 Interface and 2 pairs of Gigabit transceiver through SMA connectors.
Availability The TAI Verification Module hardware is available today.

For more information Visit www.s2ceda.com

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