TAI Player Pro 5.1 prototyping tool automatically partitions very large designs across multiple Virtex-7 3D FPGAs | Xilinx
Sep 09, 2014

TAI Player Pro 5.1 prototyping tool automatically partitions very large designs across multiple Virtex-7 3D FPGAs

by Xilinx Employee on ‎09-09-2014 10:27 AM (2,016 Views)

S2C’s TAI Player Pro is a GUI-based tool that partitions large logic designs across multiple FPGAs and then maps these designs to the company’s TAI Logic Modules based on Xilinx Virtex-7 2000T 3D FPGAs. The latest version of TAI Player Pro, version 5.1, automatically inserts LVDS pin multiplexing among the FPGAs to improve emulation performance. After mapping the design to the TAI Logic Module, the TAI Player Pro GUI monitors and controls the running prototype. The tool handles single-board TAI Logic Module configurations with 1, 2, and 4 FPGAs per module and can also map and route designs across multiple TAI Logic Modules.


One of S2C’s QuadE V7 TAI Logic Modules can pack system designs as large as 80M ASIC gates into its four on-board Xilinx Vitex-7 2000T FPGAs. You can populate the module’s four on-board DDR3 SO-DIMM sockets with as much as 32GB of DDR3 memory. The QuadE V7 TAI Logic Module supports 48 channels of high-speed 10Gbps transceivers. You can use these transceivers to implement a variety of high-speed interfaces including PCIe, SATA, and XAUI. A USB2.0 port serves as a download port for FPGA configurations and the new QuadE V7 TAI Logic Module also supports runtime features through an Ethernet connection to permit remote operation via the Internet or other IP networks. Here’s a block diagram of the S2C QuadE V7 TAI Logic Module:



 S2C QuadE V7 TAI Logic Module Block Diagram.jpg



S2C reports that one of its customers has already used these tools to partition a 300M-gate design over 24 FPGAs.

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