SAN JOSE, CA – October 28, 2021
Eight VU19P FPGAs delivering 392M ASIC gates per system and over 3 billion ASIC gates in fully populated server rack
Enhanced TransLink using MCIO to provide abundant GTY connections at up to 28Gbps for scalable FPGA interlinking and flexible topologies
Integrated High-Speed Transceiver Pin Multiplexing (HSTPM) IP support to simplify pin-muxing over GTY transceivers and maximize FPGA interlinking
Enterprise-class reliability with redundant power supplies and optimized cooling
S2C, a world leader in FPGA-based prototyping solutions today announced the release of Logic Matrix LX2, designed to satisfy the demands of enterprise prototyping that requires both high-capacity and high-performance.
Built on the Virtex UltraScale+ VU19P – Xilinx's largest and fastest UltraScale+ FPGA – the LX2 is ideal for verifying both hardware and software components of hyperscale designs ranging into the billions of ASIC gates. Holding up to 8 FPGAs in a single enclosure, the LX2 can be used stand-alone or deployed in a standard server rack with up to eight LX2s totaling 64 FPGAs. The system can be scaled even further by interconnecting LX2s over multiple racks to create a platform rivaling the capacity of many emulation systems – with 10 to 20 times the speed.
Logic Matrix address high-performance prototyping by providing a flexible connectivity architecture with 3 levels of hierarchy: ShortBridge with interconnection modules between neighboring FPGAs; SysLink to connect FPGAs over high bandwidth cables, and TransLink for longer distance links between FPGA SerDes over MCIO cables. The LX2 boosts TransLink to the next level with more abundant and faster SerDes connections. For each VU19P FPGA on the LX2, not only are 80 GTY SerDes made available over 20 MCIO connectors to accommodate scalable interlinking, MCIO connectors are adapted to support GTY at up to 28Gbps for reduced latency and higher system performance. To further simplify inter-FPGA linkage and maximize the value of TransLink, S2C's partitioning flow supports Xilinx’s newly introduced High-Speed Transceiver Pin Multiplexing (HSTPM) IP. Cycle-accurate signal transfer, pinmuxing, and low-latency SerDes connectivity between FPGAs are now made simple!
“Xilinx continues to innovate to address the needs of the Emulation and Prototyping market, not only with silicon but with tools and IPs as well,” stated Chris Stinson, senior director Test, Measurement and Emulation Markets at Xilinx. “We are excited to see the Xilinx UltraScale+ VU19P being adopted by S2C's latest Logic Matrix LX2. LX2's high density octal VU19P architecture and SerDes-rich implementation, together with the HSTPM IP, combine to make LX2 a high performing and highly scalable prototyping platform.”
Constructed to ensure high reliability and robust operation, the LX2 addresses enterprise-class considerations including real-time system monitors, efficient cooling, and redundant hot-pluggable power supplies. The Logic Matrix also comes with S2C's Player Pro Runtime software, an integrated tool providing convenient features such as advanced clock management, integrated self-test, automatic board detection, I/O voltage programming, multiple FPGA downloads, and remote system monitoring & management. Also included is AXEVision, a built-in AXI-over-Ethernet debugging tool to simplify remote debugging of AXI related designs. For advanced debugging, the LX2 supports S2C's MDM Pro, an add-on that provides deep trace debugging and cross-triggers for up to eight FPGAs.
"Today's hyperscale designs now range into the billions of ASIC gates,” said Toshio Nakama, CEO of S2C. "These complex designs are demanding - and they demand an FPGA prototyping platform that is high-performing, scalable, and robust. LX2 combines the largest FPGA available from Xilinx with an architecture designed for interconnect optimization. Combined with enterprise-class design and productivity tools, the result is an unmatched ability to deliver both performance and scalability and shorten the verification cycle. With LX2 there is no compromise.”