Connecting the "Virtual" and the "Real" for Hybrid Verification to Accelerate the SoC Design Process
Sep 03, 2020

There is a continued push to start SoC design verification earlier in the SoC design process with the SoC design and the verification environment all represented as virtual models in software. As the SoC design matures, the SoC design is gradually moved to a hardware representation in an FPGA prototype, while much of the verification environment continues to be represented in software on the host—— enabling a "hybrid" verification environment with part of the verification platform modeled in hardware and part in software. The verification environment, often as sophisticated as the design itself, must be developed to support comprehensive SoC design verification that enables maximum verification coverage prior to committing the SoC design to silicon. The goals of hybrid verification are more realistic SoC modeling, higher verification performance, and higher verification coverage. To achieve effective hybrid verification, the SoC design model and the verification environment model can be integrated to accommodate a seamless migration of the SoC design model into a hardware representation in FPGAs as the SoC design matures and bug discovery rates decline.

S2C's Prodigy™ ProtoBridge™ 3.0 integrates a virtual verification environment model in software with a hardware model of the SoC in FPGAs, enabling hybrid verification and early software development.

Prodigy ProtoBridge 3.0 uses a high-speed PCIe port on a host computer, together with an PCIe/AXI bridge in the FPGA hardware, to communicate between the virtual models on the host and hardware models in the FPGA prototype, enabling high-speed transaction-level data to be transferred between the PC host and the FPGA prototype.

Prodigy ProtoBridge 3.0 enables users to:

    • Use ESL transaction-level models on the host to verify the hardware SoC model in the FPGA for more accurate system-level verification

    • Integrate virtual verification models with FPGA-based hardware verification models to maximize overall verification performance and verification coverage

    • Realize high-performance execution of system-level models through a high-speed interface between the host and the FPGA prototype

PB 3.0 features:

    • Off-the-shelf solution for implementing a hybrid verification environment for SoC designs

    • High-speed data transfers up to 4 Giga Bytes per second between the host and the FPGA prototype

    • A library of C-API functions that can be called by software running on the host

    • Supports Windows, Ubuntu14 and RHEL6 operating systems

Media Contact

Amy Gong

MARCOM Manager


Request for Quote

What type of chip are you designing?
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
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Intel S10-2800
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Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
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