SonicBrain A10P FPGA Accelerator

SonicBrain’s A10P FPGA Accelerator is a 3/4-length PCIe x8 card based on the Intel Arria 10 GX1150 FPGA. The Arria 10 FPGAs include high-speed transceivers, embedded Gen3 PCIe x8 and massive number of IEEE 754 compliant hard floating-point DSP blocks that deliver up to 1.5 TFLOPS. The A10P offers flexible memory configurations supporting up to 32GB of memory and four front panel QSFP cages for 4x 40GbE or 16x 10GbE. All these features make the A10P a powerful PCI-Express computing and I/O platform for FPGA development and deployment across a wide range of applications, including High Performance Computing, AI, Machine Learning, Network Acceleration, Computer & Storage, Broadcast and Data Analytics.


I/O Architecture

Board Specification


  • Intel Arria 10 GX1150 FPGA
  • 1,150K Logic Elements
  • 53Mb of embedded memory
  • 3,036 18*19 variable-precision multipliers


  • Two DDR4 SO-DIMM (up to 32GB, speeds up to 2133MT/s, support ECC and Non-ECC)
  • QDR support through DDR4 SO-DIMM
  • 512Mb QSPI Flash memory for FPGA configuration

QSFP Cages

  • 4 QSFP cages on front panel
  • Each support 40GbE or 4 10GbE
  • Each high-speed transceiver can run up to 16Gbps

PCIe Interface

  • PCIe edge connector for x8 Gen3

Clock and Reset

  • 4 programmable clocks (0.16 ~ 350MHz)
  • 1 programmable clocks (10 ~ 810MHz)
  • One 100MHz LVCOMS18 oscillator
  • One 200MHz differential oscillator
  • One global reset

FPGA Configuration

  • Built-in USB Blaster II interface for JTAG access
  • Power-on FPGA configuration from QSPI 512Mb Flash
  • Remote Partial Reconfiguration through PCIe (CvP)

System Management

  • System Management utility through USB port or PCIe Sideband
  • Clock Configuration
  • Voltage, current and temperature monitoring
  • Auto shut-down upon detection of over-current

Board Size

  • Length: 241.3mm (9.5 inches)
  • Height: 111.28mm (4.38 inches) / Standard Height PCIe
  • Single Width

Development Kit Contents (Optional)

SonicBrain’s Development Kits radically cuts development time and reduce project risk by using pre-tested and configurable modules.

AXI-Based HDL Development Kit

  • AXI-4 interconnection module and Master/Slave interfaces for FPGA design integration
  • A set of C-API function calls to perform AXI bus transactions in the host computer
  • PCIe driver for Linux or Windows operating systems
  • C-API reference operations with sample DMA access to DDR4 memory up to 4GB/s
  • System integration guide to connect user RTL code with the AXI-4 bus module

Reference Designs

  • DDR4 reference design
  • XCVR loopback test design on QSFP port



Arria 10 GX1150

Arria 10 GX660

  Logic Elements (K)
  M20K memory (Mb)
  18 x 19 multipliers
  PCIe Gen3 Support